1. Field of the Invention
This invention pertains in general to portable electronic devices and in particular to reducing power consumption of such devices by controlling the clock frequencies in the devices.
2. Background of the Invention
The need for portable electronic devices, also referred to as “electronic appliances” is growing rapidly. Numerous small devices, such as the PALM PILOT organizer from 3COM, INC. and MICROSOFT WINDOWS CE-based palm computers have become ubiquitous in society. As the sizes of the devices decrease and the processing powers increase, these devices will become even more prevalent. For example, solid-state music players, smart phones, screen phones, digital cameras, and other Internet-ready electronic appliances will soon become mainstream.
By nature, a portable electronic device should be as small and light as possible. Accordingly, there is a desire to reduce the amount of circuitry within the device by combining functions previously performed by separate integrated circuits (ICs) into a single complementary metal oxide semi-conductor (CMOS) application specific integrated circuit (ASIC). For example, a single ASIC for a portable electronic device may include a central processing unit (CPU), a digital signal processor (DSP), a peripheral controller, a memory controller, a video controller, a clock controller, and an interrupt controller.
However, the CMOS ASIC requires a significant amount of power to provide this functionality. Since the battery is often one of the heaviest and bulkiest components of a portable electronic device, there is a strong desire to minimize power consumption by the ASIC and other components. Although a single ASIC typically uses less power than do separate ICs, there is a desire to reduce the power use even further.
For example, in a CMOS ASIC, the majority of power dissipation is due to the alternating current (AC) element that results from the charging and discharging of the capacitance in the chip. The power dissipation of a typical logic gate in a CMOS ASIC is approximated by the following equation:Power Dissipation=Vdd2·C·Freq; where Vdd is the voltage supply to a logic gate, C is the total intrinsic and extrinsic capacitance loading to the logic gate, and Freq is the toggle frequency of the logic gate. The total power dissipation of the CMOS ASIC is the sum of all power dissipated at each logic gate at the gate's respective toggle frequency and total capacitance loading.
Thus, the major power draws on the ASIC are the clocks generated by the clock controller and the digital logic that is controlled directly or indirectly by the clocks. A typical clock controller, for example, may generate separate clocks for driving the CPU, system·bus, memory; and peripherals. The operating speed of the driven device is dependent on the frequency of its clock. Since there is a general desire to operate the device at its highest speed, the clocks are usually run at a high frequency and therefore dissipate power at a high rate.
Moreover, if a device is operated with a clock frequency higher than is necessary, the power utilized to operate at the higher-frequency clock is essentially wasted. For example, the system memory may run on a 100 MHz clock. However, an external peripheral accessing the memory, such as an infra-red (IR) transceiver, may support data transfers at only a fraction of the speed of which the memory is capable. Assuming that there are on concurrent memory requests from other devices, the power needed to drive the system memory at a higher frequency than is needed to support the IR transceiver is essentially wasted.
Some ASICs contain special circuitry to reduce power consumption by disabling external memory devices using the “CKE” signal when there are no memory accesses. While the external memory devices save power by entering a low power state when disabled, the memory clock generated by the clock controller remains running at full speed. In addition, the “Clock I/O” pin to the external memory also toggles continuously, thereby consuming power on the clock driver I/O pad and the clock receiver I/O pads.
Accordingly, there is a need for a low-power CMOS ASIC for a portable electronic device. Preferably, the ASIC would minimize power wasted by free running clocks and mismatches between the bandwidth requirements of different devices. The ASIC should also achieve these goals without sacrificing system performance.